1. Field of the Invention
The present invention relates to a method of fabricating an integrated bipolar planar transistor whose base region is formed by ion implantation through an insulating layer of a given thickness and composition deposited on a semiconductor body, and whose emitter region is also formed by ion implantation.
2. Description of the Prior Art
This type of method is disclosed in European Patent Application No. 0 002 661. In this known method, prior to a final heat treatment between 900.degree. C. and 1,100.degree. C. for annealing lattice imperfections, both the base dopant and the emitter dopant are introduced into the semiconductor surface and activated. Since the initially deposited insulating layer now remains on the semiconductor surface at least in the area of the metallized interconnection pattern, and no reoxidation takes place, lead capacitance variations are relatively small.
However, the known method has a disadvantage in that the base widths and, thus, the current gains of the bipolar planar transistors which are simultaneously fabricated on a semiconductor wafer are subject to variations. These variations correspond to the oxide-thickness variations if the base dopants are not implanted in two implantation processes at different acceleration energies, during which a drift field is produced which retards the movement of the minority carriers, because the base dopant is implanted through an insulating layer made of silicon oxide, while the emitter dopant is introduced directly into the semiconductor surface.